reduce_logical_and.hpp
1 // Copyright (C) 2018-2021 Intel Corporation
2 // SPDX-License-Identifier: Apache-2.0
3 //
4 
5 #pragma once
6 
7 #include "ngraph/op/util/logical_reduction_keep_dims.hpp"
8 
9 namespace ngraph
10 {
11  namespace op
12  {
13  namespace v1
14  {
15  /// \brief Performs a reduction using "logical and"
16  ///
17  /// The reduction is performed over slices of the first input. The slices shape depends
18  /// on the values passed to the second input - the axes.
20  {
21  public:
22  NGRAPH_RTTI_DECLARATION;
23  ReduceLogicalAnd() = default;
24  /// \brief Constructs a ReduceLogicalAnd node.
25  ///
26  /// \param data - The input tensor with data to be reduced
27  /// \param reduction_axes - The input tensor with information about axes over which
28  /// the first tensor should be sliced prior to the reduction operation
29  /// \param keep_dims - Indicates if the axes used for reduction should be held/kept
31  const Output<Node>& reduction_axes,
32  const bool keep_dims = false);
33 
34  virtual std::shared_ptr<Node>
35  clone_with_new_inputs(const OutputVector& new_args) const override;
36 
37  bool evaluate(const HostTensorVector& outputs,
38  const HostTensorVector& inputs) const override;
39  bool has_evaluate() const override;
40  };
41  } // namespace v1
42  } // namespace op
43 } // namespace ngraph
A handle for one of a node's outputs.
Definition: node_output.hpp:33
Definition: logical_reduction_keep_dims.hpp:17
Performs a reduction using "logical and".
Definition: reduce_logical_and.hpp:20
ReduceLogicalAnd(const Output< Node > &data, const Output< Node > &reduction_axes, const bool keep_dims=false)
Constructs a ReduceLogicalAnd node.
bool evaluate(const HostTensorVector &outputs, const HostTensorVector &inputs) const override
Evaluates the op on input_values putting results in output_values.
bool has_evaluate() const override
Allows to get information about availability of evaluate method for the current operation.
The Intel nGraph C++ API.
Definition: attribute_adapter.hpp:16